The present invention relates to electrically erasable memory systems and in particular to a high speed, nonvolatile, electrically erasable memory cell and system.
Piror art nonvolatile memory systems have been restricted to field effect transistor, typically MOS, technology with a resultant limitation in operating speed. While it is well known that higher operating speeds are provided by bipolar technology, prior bipolar art has lacked a nonvolatile storage mechanism.
The present invention provides a process wherein a series of steps utilizable for fabricating complete bipolar circuit elements is supplemented by steps which result in a nonvolatile memory cell. Thus, according to the present invention, an electrically erasable nonvolatile memory array is provided which may be readily fabricated on the same chip with high speed bipolar driving, decoding and sensing circuits utilizing a minimum number of process steps.